Traditional positive and negative edge triggered scan design requires precise control of the time scan and actual data is presented to and transferred from the latches of scan chains. These requirements create a burden in the chip design cycle, in that the chip designer must ensure that all signals in the scan chain path and data path arrive at the latch after the clock edge arrives. This is generally accomplished using external circuitry. Thus the present methodologies are time-consuming to implement and utilize relatively complicated circuitry. Therefore, there is a need for a methodology that overcomes the need for external circuitry and reduces the burden on the designer.